Multilevel copper interconnects for ultra large scale integration
US6593656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2002 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Jan 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76879
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing integrated circuits using a thin metal oxide film as a seed layer for building multilevel interconnects structures in integrated circuits. Thin layer metal oxide films are deposited on a wafer, and standard optical lithography is used to expose the metal oxide film in a pattern corresponding to a metal line pattern. The metal oxide film is converted to a layer of metal, and a metal film may then be deposited on the converted oxide film by either selective CVD or electroless plating. Via holes are then fabricated in a similar process using via hole lithography. The process is continued until the desired multilevel structure is fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.