Data processing system with HSA (hashed storage architecture)
US6598118B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having a hashed and partitioned storage subsystem includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a cache subsystem including a plurality of caches that store data utilized by the execution unit. Each cache among the plurality of caches stores only data having associated addresses within a respective one of a plurality of subsets of an address space. In one preferred embodiment, the execution units of the processor include a number of load-store units (LSUs) that each process only instructions that access data having associated addresses within a respective one of the plurality of address subsets. The processor may further be incorporated within a data processing system having a number of interconnects and a number of sets of system memory hardware that each have affinity to a respective one of the plurality of address subsets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.