Methods of forming capacitors, and methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions
US6599800B2 · kind B2 · utility
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13References
50Claims
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Key dates
| Filing date | Sep 14, 2001 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Sep 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
Abstract
Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.