Making leadframe semiconductor packages with stacked dies and interconnecting interposer
US6603072B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2001 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Apr 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a leadframe type of semiconductor package, the internal electrical interconnectability of and signal routing between multiple dies laminated in a stack with the die paddle of the leadframe is substantially enhanced by laminating an “interposer” in the stack. The interposer comprises a dielectric layer and a metallic layer patterned to include wire bonding pads arrayed around the periphery of a surface thereof, and circuit traces interconnecting selected ones of the wire bonding pads in a single plane across the horizontal span of the interposer. In packages having multiple dies and relatively few leads, the bonding pads and circuit traces can be flexibly arranged on the interposer by the package designer to substantially increase the number and routings of internal electrical interconnections otherwise possible between the dies and between the dies and the leads of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.