Predictive timing calibration for memory devices
US6606041B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2000 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | May 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A unique way of using a 2N bit synchronization pattern to obtain a faster and more reliable calibration of multiple data paths in a memory system is disclosed. If the 2N bit synchronization pattern is generated with a known clock phase relationship, then the data-to-clock phase alignment can be determined using simple decode logic to predict the next m-bits from a just-detected m-bits. If the succeeding m-bit pattern does not match the predicted pattern, then the current data-to-clock alignment fails for a particular delay value adjustment in the data path undergoing alignment, and the delay in that data path is adjusted to a new value. All data alignment is ensured to occur to a desired edge of the clock signal, e.g., a positive going edge, by forcing a failure of all predicted m-bit patterns which are associated with an undesired edge, e.g., a negative going edge, of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.