Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same
US6610560B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2001 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | May 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor packaging technology is proposed for the fabrication of a chip-on-chip (COC) based multi-chip module (MCM) with molded underfill. The proposed semiconductor packaging technology is characterized by the provision of a side gap of an empirically-predetermined width between the overlying chips mounted through COC technology over an underlying chip to serve as an air vent during molding process. This allows the injected molding material to flow freely into the flip-chip undergaps during molding process. In actual application, the exact width of the side gap is empirically predetermined through molded-underfill simulation experiments to find the optimal value. Based on experimental data, it is found that this side gap width should be equal to or less than 0.3 mm to allow optimal underfill effect. The optimal value for this side gap width may be varied for different package specifications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.