Forming dual gate oxide thickness on vertical transistors by ion implantation

US6610575B1 · kind B1 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Chew Hoe Ang · Singapore, SG
• Eng Hua Lim · Singapore, SG
• Cher Liang Cha · Singapore, SG
• Jia Zhen Zheng · Singapore, SG
• Elgin Quek · Singapore, SG
• Mei Sheng Zhou · Singapore, SG
• Daniel Yen · Singapore, SG

Key dates

• Filing date: Jun 4, 2002
• Grant date: Aug 26, 2003
• Expiry date: Jun 4, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0195

Abstract

A method of structures having dual gate oxide thicknesses, comprising the following steps. A substrate having first and second pillars is provided. The first and second pillars each having an outer side wall and an inner side wall. At least one of the outer or inner side walls of at least one of the first and second pillars is/are masked leaving at least one of the outer or inner side walls of at least one of the first and second pillars exposed. Dopants are then implanted through the at least one of the exposed outer or inner side walls modifying the surface of the at least one of the doped exposed outer or inner side walls. The at least one of the masked outer or inner side walls of at least one of the first and second pillars is/are unmasked. Gate oxide is grown on the outer side walls and the inner side walls of the first and second pillars wherein the gate oxide grown upon the modified surfaces of the at least one of the doped outer or inner side walls is thicker than the gate oxide grown upon the non-modified surfaces of the at least one of the non-doped outer or inner side walls.