Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask
US6610604B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2002 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Mar 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28132
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.