Chip edge interconnect apparatus and method
US6611050B1 · kind B1 · utility
48Cited by
19References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2000 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Mar 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of forming a low profile chip interconnection, and the interconnection so formed. A recessed contact area is formed at an edge of the wafer. A conductive material is deposited within the adjacent contact areas of each recess, thereby electrically connecting the two chips. The recess may have substantially perpendicular sides, or sloped sides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.