BPSG, SA-CVD liner/P-HDP gap fill

US6613657B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Minh Van Ngo · Fremont, US
• Dawn Hopper · San Jose, US
• Wenmei Li · San Jose, US
• Kelwin Ko · San Jose, US
• Kuo-Tung Chang · Saratoga, US
• Tyagamohan Gottipati · Sunnyvale, US

Key dates

• Filing date: Aug 30, 2002
• Grant date: Sep 2, 2003
• Expiry date: Aug 30, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

Device leakage due to spacer undercutting is remedied by depositing a BPSG, SA-CVD oxide liner and flowing it into the undercut regions, followed by gap filling with a P-doped HDP oxide layer. Embodiments include depositing a BPSG, SA-CVD oxide liner containing 4 to 6 wt.% boron, at a thickness of 1,000 å to 1,800 å, over closely spaced apart non-volatile transistors and heating during or subsequent to deposition to flow the BPSG, SA-CVD oxide liner into the undercut regions of the sidewall spacers of the gate stacks. Gap filling is then completed by depositing the layer of P-doped HDP at a thickness of 6,000 å to 10,000 å.