Wet etch reduction of gate widths
US6617085B1 · kind B1 · utility
8Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2002 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Aug 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a desired gate length and etching the etch-control layer and the hardmask layer; the portion of the circuit that has the correct gate length is covered with a blocking mask and the hardmask in the remainder is wet-etched to reduce its dimension, after which the gate stack is etched using both gate lengths of hardmask to produce different gate lengths in different areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.