Semiconductor device and a method of manufacturing the same
US6617632B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2001 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Jan 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel connection-type nonvolatile memory semiconductor device comprises a plurality of memory cells disposed on a semiconductor substrate in matrix form, each including a gate insulating film, a floating gate electrode, an interlayer film and a control gate electrode successively formed so as to cover a channel region on a main surface of the semiconductor substrate, of a first conductivity type; a second conductivity type source and drain regions formed on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing a second conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially lower than the drain region in impurity concentration; and a punch-through stopper layer which is adjacent to the first semiconductor region and formed by introducing a first conductivity type impurity in the direction of the channel region plac…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.