Method for forming inside nitride spacer for deep trench device DRAM cell
US6620699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Sep 16, 2003 |
| Priority date | — |
| Expiry date | Sep 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide layer under the pad nitride layer, and a recessed gate poly in the trench. The method further includes depositing a spacer material on the oxide liner, removing exposed portions of the oxide layer from the semiconductor, and depositing a poly stud material over the semiconductor wherein the spacer material is encapsulated in poly stud material. The method includes polishing the semiconductor to the top trench oxide layer, and etching the top trench oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.