Memory cell arrangement

US6627940B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Dirk Schumann · Lübbenau/Spreewald - Lubnjow/Błota, DE
• Bernhard Sell · Dresden, DE
• Hans Reisinger · Grünwald, DE
• Josef Willer · Riemerling, DE

Key dates

• Filing date: Feb 5, 2002
• Grant date: Sep 30, 2003
• Expiry date: Feb 5, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/34

Abstract

A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.