On-chip repair of defective address of core flash memory cells
US6631086B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2002 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Jul 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method and system for repairing defective flash memory cells fabricated on a semiconductor substrate, a repair controller and a plurality of voltage sources are fabricated on the semiconductor substrate. The repair controller controls the voltage sources to apply programming voltages on respective CAM (content addressable memory) flash memory cells in a JUICE state for replacing the defective flash memory cells with a corresponding redundancy element of flash memory cells. In addition, a FAILREP logic is fabricated on the semiconductor substrate for entering a HANG state if no redundancy element of flash memory cells is available or if the defective flash memory cells have been previously repaired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.