Method of fabricating variable length vertical transistors
US6632712B1 · kind B1 · utility
49Cited by
6References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2002 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Oct 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.