Methods of forming gated semiconductor assemblies
US6635530B2 · kind B2 · utility
7Cited by
53References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1998 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Apr 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
The invention includes a method of forming a gated semiconductor assembly. A first transistor gate layer is formed over a substrate. A silicon nitride layer is formed over the first transistor gate layer. The silicon nitride layer comprises a first portion and a second portion elevationally displaced above the first portion. The first portion has less electrical resistance than the second portion and a different stoichiometric composition than the second portion. The first portion is physically against the second portion. A second transistor gate layer is formed over the silicon nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.