DRAM cell constructions

US6639243B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Fernando Gonzalez · Boise, US
• Kevin L. Beaman · Boise, US
• John T. Moore · Boise, US
• Ron Weimer · Boise, US

Key dates

• Filing date: Dec 5, 2001
• Grant date: Oct 28, 2003
• Expiry date: Dec 13, 2021

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/906

Abstract

The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate having a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further includes a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.