Memory chip having a test mode and method for checking memory cells of a repaired memory chip
US6639856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | May 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory chip has regular memory cells and standby memory cells for replacing faulty memory cells. There is provided a method for checking memory cells of a repaired memory chip, where the memory cells are checked by putting the memory chip into the state before repair. This actuates the memory cells identified as being faulty in spite of the provision of standby memory cells. This allows the operability of the memory chip to be checked after the repair procedure has been carried out. It is thus possible to identify, by way of example, whether a fault has been produced by the repair procedure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.