Patent · US Expired

Integrated memory and method for testing an integrated memory

US6639861B2 · kind B2 · utility

3Cited by

2References

7Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Reidar Stief · Birkenfeld, DE
Peter Beer · Waldshut-Tiengen, DE
Herbert Benzinger · Birkenfeld, DE
Stephan Schroeder · Munich, DE

Key dates

Filing date	Apr 18, 2002
Grant date	Oct 28, 2003
Priority date	—
Expiry date	Apr 18, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/02
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated memory has a memory cell array containing word lines and bit lines. The bit lines, for reading out a data signal, can in each case be connected to a sense amplifier via a controllable switching device. Furthermore, a control circuit is contained, having an output, which is connected to a control input of the respective switching device, and having an input, which is connected to a terminal for a test mode signal. The control circuit is configured in such a way that, within an access cycle, the respective switching device can be switched into a non-conducting state on account of an active state of the test mode signal. In the integrated memory, it is possible to measure the leakage behavior of a bit line during the read-out of a data signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.