Salicided gate for virtual ground arrays
US6645801B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2001 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Oct 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a process for saliciding the word lines in a virtual ground array flash memory device without saliciding the substrate between word lines. According to the invention, in a process for manufacturing virtual ground array flash memory devices, a salicide protect layer covers the substrate between word lines in the core region while the tops of the word lines are exposed. The salicide protect layer can be brought into the desired configuration by one or more of masking the substrate between word lines during an etching process, removing salicide protection material in the core by polishing, and forming a comparatively thick layer of salicide protection material in the core whereby the tendency of the salicide protect layer to follow the contour of the underlying structures is reduced. With the substrate between word lines protected by the salicide protect layer, the word lines are salicided. The process of the invention produces virtual ground array flash memory devices with salicided word lines, but without shorting between bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.