Flash memory array architecture having staggered metal lines
US6646914B1 · kind B1 · utility
24Cited by
8References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2002 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Mar 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes a plurality of sets of transistors, each set including a pair of transistors in series. Each such pair of transistors is connected between a pair of adjacent bit lines. Each of the pair of transistors in each set is associated with a different one of an adjacent pair of word lines. The array is configured by providing substantially strait elongated source/drain regions in side-by-side, parallel relation. Each bit line has a zigzag configuration and connects to a pair of adjacent source/drain regions in alternating manner along the bit line length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.