Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
US6649470B2 · kind B2 · utility
2Cited by
25References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | May 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5612
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while source and drain regions are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. Methods of fabricating the memory cell and operating it are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.