Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol
US6654858B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Nov 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system has a plurality of processors wherein each processor preferably has its own cache memory. Each processor or group of processors may have a memory controller that interfaces to a main memory. Each main memory includes a “directory” that maintains the directory coherence state of each block of that memory. One or more of the processors are members of a “local” group of processors. Processors outside a local group are referred to as “remote” processors with respect to that local group. Whenever a remote processor performs a memory reference for a particular block of memory, the processor that maintains the directory for that block normally updates the directory to reflect that the remote processor now has exclusive ownership of the block. However, memory references between processors within a local group do not result in directory writes. Instead, the cache memory of the local processor that initiated the memory requests places or updates a copy of the requested data in its cache memory and also sets associated tag control bits to reflect the same or similar information as would have been written to the directory. If a subsequent r…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.