Gate processing method with reduced gate oxide corner and edge thinning
US6656798B2 · kind B2 · utility
0Cited by
5References
8Claims
0Family size
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Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Nov 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, providing a sacrificial oxide layer by thickening said pad oxide layer to a desired oxide thickness, in using said thickened pad oxide layer as said sacrificial oxide layer for device implantation, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a final gate oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.