Configuration for measurement of internal voltages of an integrated semiconductor apparatus
US6657452B2 · kind B2 · utility
5Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2000 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Dec 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/165
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The invention relates to a configuration for the measurement of internal voltages in a DUT (2), in which a comparator (3) is provided in each DUT (2) and compares the internal voltage (Vint) to be measured with an externally supplied reference voltage (Vref).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.