Patent · US Expired

Integrated memory with memory cell array

US6657916B2 · kind B2 · utility

1Cited by

5References

9Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Heinz Honigschmid · Starnberg, DE
Stefan Lammers · Hersbruck, DE
Helmut Kandolf · Hersbruck, DE

Key dates

Filing date	Jan 22, 2002
Grant date	Dec 2, 2003
Priority date	—
Expiry date	Jan 22, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.