System latency levelization for read data
US6658523B2 · kind B2 · utility
48Cited by
9References
37Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 13, 2001 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Jul 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.