Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction
US6658556B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store units that each process only instructions that access data having associated addresses within a respective one of a plurality of subsets of an address space. The load-store units can have diverse hardware such that a maximum number of instructions that can be concurrently executed is different for different load-store units or such that some of the load-store units are restricted to executing certain classes of instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.