Stacked gate flash memory cell with reduced disturb conditions
US6660585B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2000 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Mar 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.