Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6662304B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Jan 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a plurality of digital signals applied to respective latches in the packetized memory device. A clock generator circuit generates a plurality of internal clock signals responsive to the external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal. A plurality of selection circuits are coupled to the clock generator circuit and each has an output coupled to a clock terminal of an associated latch. Each selection circuit applies one of the internal clock signals to clock the associated latch in response to a phase command signal. An evaluation circuit receives digital signals sequentially stored in a selected one of the latches and generates a results signal indicating whether each of the digital signals has an expected value. A control circuit sequentially selects the latches and operates for each selected latch to adjust the phase command signals applied to the selection circuit coupled to the selected latch and store respective result…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.