Method for fabricating a body region for a vertical MOS transistor arrangement having a reduced on resistivity

US6670244B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Helmut Gassel · Farmington Hills, US
• Werner Kanert · Holzkirchen, DE
• Helmut Strack · Hersbruck, DE
• Franz Hirler · Isen, DE
• Herbert Pairitsch · Klagenfurt, AT

Key dates

• Filing date: Aug 30, 2001
• Grant date: Dec 30, 2003
• Expiry date: Aug 30, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0291

Abstract

A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the body region has a reduced resistivity without a corresponding reduction in the breakdown voltage of the transistor. The method includes, inter alia: performing a first implantation of a doping material of a first conduction type into the semiconductor body such that an implantation maximum of the first implantation lies within the semiconductor body set back from the channel region; and performing a second implantation of a doping material of the first conduction type such that an implantation maximum of the second implantation lies within the semiconductor body below the implantation maximum of the first implantation. The dose of the second implantation is less than the dose of the first implantation.