Memory module with improved electrical properties
US6670665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2003 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Feb 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/038
Abstract
A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. First electrodes of the dummy memory cells are connected to a reference potential. A counter electrode of the dummy memory cells is electrically connected to the counter electrode of the memory cells. A charge capacitance of the counter electrode of the memory cells is increased in this way. Consequently, there is an overall increase in the voltage stability of the memory module with respect to a large entry of charge into the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.