Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits

US6670802B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Stefan Dietrich · Potsdam, DE
• Patrick Heyne · Hersbruck, DE
• Thilo Marx · Villingen-Schwenningen, DE
• Sabine Kieser · Hausham, DE
• Michael Sommer · Raubling, DE
• Thomas Hein · Hersbruck, DE
• Michael Markert · Augsburg, DE
• Torsten Partsch · San Jose, US
• Peter Schroegmeier · Birkenfeld, DE
• Christian Weis · Scheidegg, DE

Key dates

• Filing date: Oct 22, 2001
• Grant date: Dec 30, 2003
• Expiry date: Jan 2, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/003
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.