Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
US6671040B2 · kind B2 · utility
74Cited by
40References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Sep 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programming circuit includes a wordline decoder, an adjustable voltage generator, and a column transistor. The programming circuit is useful in programming a memory cell comprised of a select transistor and a data storage element. The data storage element is programmed by a programming current. The amount of the programming current can be modulated by the column transistor, the select transistor, or the adjustable voltage generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.