Integrated shallow trench isolation approach
US6677242B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2000 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Aug 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0273
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for processing a silicon substrate disposed in a substrate process chamber includes transferring the substrate into the substrate process chamber. The substrate having a hard mask formed thereon and a patterned photoresist overlying the hard mask to expose portions of the hard mask. The chamber being the type having a source power system and a bias power system. The method further includes etching the exposed portions of the hard mask to expose portions of the silicon substrate underlying the hard mask. Thereafter, the patterned photoresist is exposed to a first plasma formed from a first process gas to remove the photoresist from the hard mask. Thereafter, the exposed silicon substrate is etched by exposing the substrate to a second plasma formed from a second process gas by applying RF energy from the source power system and biasing the plasma toward the substrate. The substrate is transferred out of the substrate processing chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.