Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers
US6677679B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2001 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Feb 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a second etch top layer, a dielectric layer and an opening extending through the dielectric layer, the first and second etch stop layers, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The second etch stop layer is disposed over the first diffusion barrier layer, and the first etch stop layer is disposed on the second etch stop layer with a first interface therebetween. The dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer and the barrier diffusion layer can be formed from silicon nitride, and the second etch stop layer can be formed from silicon oxide. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclose…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.