Method and apparatus for allocating data usages within an embedded dynamic random access memory device
US6678814B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Jan 13, 2004 |
| Priority date | — |
| Expiry date | Jan 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for allocating data usage in an embedded dynamic random access memory (DRAM) device is disclosed. The apparatus for allocating data usages within an embedded dynamic random access memory (DRAM) device comprises a control analysis circuit, a data/command flow circuit, and a partition management control. The control analysis circuit generates an allocation signal in response to processing performances of a processor. Coupled to an embedded DRAM device, the data/command flow circuit controls data flow from the processor to the embedded DRAM device. The partition management control, coupled to the control analysis circuit, partitions the embedded DRAM device into a first partition and a second partition. The data stored in the first partition are different from the data stored in the second partition according to their respective usage. The allocation percentages of the first and second partitions are dynamically allocated by the allocation signal from the control analysis circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.