Process for forming a multi-level thin-film electronic packaging structure
US6678949B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2001 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Mar 20, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49213
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A structure for mounting electronic devices. The structure uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.