Translation lookaside buffer that caches memory type information
US6681311B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2001 |
| Grant date | Jan 20, 2004 |
| Priority date | — |
| Expiry date | Apr 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A translation lookaside buffer (TLB) that caches memory types of memory address ranges. A data unit includes a TLB which, in addition to caching page table entries including translated page base addresses of virtual page numbers as in a conventional TLB, also caches memory address range memory types provided by a memory type unit (MTU). In the case of a hit of a virtual address in the TLB, the TLB provides the memory type along with the page table entry, thereby avoiding the need for a serialized accessed to the MTU using the physical address output by the TLB. Logic which controls a processor bus access necessitated by the virtual address makes use of the memory type output by the TLB sooner than would be available from the MTU in conventional data units. If the MTU is updated, the TLB is flushed to insure consistency of memory type values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.