Low profile stack semiconductor package
US6683385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2002 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Jun 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low profile stack semiconductor package is proposed. A lower chip having centrally-situated bond pads is mounted on a substrate, and electrically connected to the substrate by bonding wires. A cushion member is peripherally situated on the lower chip, allowing the bonding wires to extend from the bond pads in a direction parallel to the lower chip, and to reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate. An adhesive is applied on the lower chip, for encapsulating the bond pads, cushion member and bonding wires. This allows an upper chip to be readily stacked on the lower chip by attaching the upper chip to the adhesive, without affecting or damaging structural or electrical arrangement formed on the lower chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.