Deskewing global clock skew using localized DLLs
US6686785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2001 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Oct 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.