Method and apparatus for setting and compensating read latency in a high speed DRAM
US6687185B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Aug 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock is produced from the external clock signal in a delay lock loop circuit and a start signal, produced in response to a read command, is passed through a delay circuit slaved with the delay lock loop so that the read clock signal and a delayed start signal are subject to the same internal timing variations. The delayed start signal is used to thereby control the output of read data by the read clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.