4 F2 folded bit line DRAM cell structure having buried bit and word lines

US6689660B1 · kind B1 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Wendell P. Noble · Colchester, US
• Leonard Forbes · Corvallis, US
• Kie Y. Ahn · Chappaqua, US

Key dates

• Filing date: Mar 17, 2000
• Grant date: Feb 10, 2004
• Expiry date: Mar 17, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/34

Abstract

A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transistors of adjacent memory cells, and a pair of word lines are located in each of the isolation trenches. The word lines are oriented vertically widthwise in the trench and are adapted to gate alternate access transistors, so that both an active and a passing word line can be contained within each memory cell to provide a folded bit line architecture. The memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Also disclosed are processes for fabricating the DRAM cell using bulk silicon or a silicon on insulator processing techniques.