Transistor configuration with a shielding electrode outside an active cell array and a reduced gate-drain capacitance

US6690062B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ralf Henninger · Birkenfeld, DE
• Franz Hirler · Isen, DE
• Joachim Krumrey · Eisenlohrsweg, AT
• Walter Rieger · Arnoldstein, AT
• Martin Poelzl · Ossiach, AT

Key dates

• Filing date: Mar 19, 2003
• Grant date: Feb 10, 2004
• Expiry date: Mar 19, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/252

Abstract

The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.