DRAM cell constructions
US6707090B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2003 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Mar 20, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/906
Abstract
The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate containing a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further contains a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.