Method of forming semiconductor device including interconnect barrier layers

US6713381B2 · kind B2 · utility

Assignee

• Motorola, Inc. · US

Inventors

• Alexander L. Barr · Austin, US
• Suresh Venkatesan · Los Gatos, US
• David B. Clegg · Austin, US
• Rebecca G. Cole · Austin, US
• Olubunmi O. Adetutu · Austin, US
• Stuart E. Greer · Shelburne, US
• Brian G. Anthony · Austin, US
• Ramnath Venkatraman · San Jose, US
• Gregor Braeckelmann · Austin, US
• Douglas M. Reber · Austin, US
• Stephen Crown · Austin, US

Key dates

• Filing date: Jan 18, 2002
• Grant date: Mar 30, 2004
• Expiry date: Jan 18, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3025
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).