Stacked chip package with enhanced thermal conductivity
US6713856B2 · kind B2 · utility
82Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Sep 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked chip package has a substrate with a through hole. A first chip is received in the through hole. A second chip is disposed on the first chip. Two chips are electrically connected to an upper surface of the substrate. An adhesive layer and a planar member, which are thermally and electrically conductive, are disposed on a lower surface of the substrate to support the chips and dissipate the heat generated by the chips. An encapsulant covers the upper surface of the substrate. The package has superior heat-dissipating ability, high yield in assembly and small size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.