Memory architecture with memory cell groups
US6724026B2 · kind B2 · utility
6Cited by
3References
13Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Sep 19, 2002 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Sep 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process instead of two, as conventionally required. In one embodiment, each capacitor of a capacitor pair is provided with at least one plug contacting a common diffusion region of two adjacent cell transistors. In another embodiment, a large plug with sufficient overlap to the bottom electrodes of pair of capacitors is used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.