Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling
US6727545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2001 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Jul 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations or different widths. The trenches are filled with a conducting material to form blocks of the conducting material that constitute source regions with a first portion that is disposed adjacent to but insulated from the floating gate, and a second portion that this disposed over but insulated from the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.